More whitespace changes

data/nextreg.txt

@@ -1199,40 +1199,40 @@ progress is made in the main program.
 --
 
 0xF0 (240) => XDEV CMD
-(R/W Issue 4 Only) (soft reset = 0x80)
-   * Select Mode
-     (R)
-       bit 7 = 1 if in select mode
-       bits 1:0 indicate currently selected device
-         00 = none
-         01 = Xilinx DNA
-         10 = Xilinx XADC
-     (W)
-       bit 7 = 1 to enter select mode, 0 to enter selected device mode (no other bits have effect)
-       bit 6 = 1 to change selected device
-       bits 1:0 selected device
-         00 = none
-         01 = Xilinx DNA
-         10 = Xilinx XADC
-   * Xilinx DNA Mode
-     (R)
-       bit 0 = dna bit (serial stream shifts left)
-       the first eight bits read will indicate the length of the following dna bits
-     (W)
-       bit 7 = 1 to enter select mode (write has no other effect)
-       otherwise causes dna string to reload, ready for fresh read
-   * Xilinx XADC Mode (Documented in Xilinx Series 7 UG480)
-     (R)
-       bit 6 = 1 if XADC is busy with conversion (BUSY)
-       bit 1 = 1 if XADC conversion completed since last read (EOC, read clears)
-       bit 0 = 1 if XADC conversion sequence completed since last read (EOS, read clears)
-     (W)
-       bit 7 = 1 to enter select mode (write has no other effect)
-       bit 6 = 1 to reset XADC (RESET)
-       bit 0 = 1 to start conversion (CONVST)
+R/W Issue 4 Only - (soft reset = 0x80)
+  Select Mode
+    (R)
+      bit 7 = 1 if in select mode
+      bits 1:0 = indicate currently selected device
+        00 = none
+        01 = Xilinx DNA
+        10 = Xilinx XADC
+    (W)
+      bit 7 = 1 to enter select mode, 0 to enter selected device mode (no other bits have effect) ***
+      bit 6 = 1 to change selected device **
+      bits 1:0 = selected device
+        00 = none
+        01 = Xilinx DNA
+        10 = Xilinx XADC
+  Xilinx DNA Mode
+    (R)
+      bit 0 = dna bit (serial stream shifts left)
+        the first eight bits read will indicate the length of the following dna bits
+    (W)
+      bit 7 = 1 to enter select mode (write has no other effect) *
+        otherwise causes dna string to reload, ready for fresh read
+  Xilinx XADC Mode (Documented in Xilinx Series 7 UG480)
+    (R)
+      bit 6 = 1 if XADC is busy with conversion (BUSY)
+      bit 1 = 1 if XADC conversion completed since last read (EOC, read clears)
+      bit 0 = 1 if XADC conversion sequence completed since last read (EOS, read clears)
+    (W)
+      bit 7 = 1 to enter select mode (write has no other effect) *
+      bit 6 = 1 to reset XADC (RESET)
+      bit 0 = 1 to start conversion (CONVST)
   * Re-enter select mode at any time by writing to the register with bit 7 set
-  * Select a device to communicate with by writing to the register with bits 6 & 7 set
-  * Exit select mode by writing zero to bit 7; thereafter the particular device is attached to the nextreg
+  ** Select a device to communicate with by writing to the register with bits 6 & 7 set
+  *** Exit select mode by writing zero to bit 7; thereafter the particular device is attached to the nextreg
 
 0xF8 (248) => XADC REG
 (R/W Issue 4 Only) (hard reset = 0)