Attempt for project to document itself, and moving to live version of nextreg.txt
This commit is contained in:
259
data/nextreg.txt
259
data/nextreg.txt
@@ -1,11 +1,26 @@
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The ZX Next stores configuration state in a field of registers.
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These registers are accessible via two io ports or via the special nextreg instructions.
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Port 0x243B (9275) is used to select the register by number, listed below.
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Port 0x253B (9531) is used to read or write the register value.
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Some registers are accessible only during the initialization process.
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Registers 0x80 and above are inaccessible to the copper.
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Initial values are set during a hard or soft reset but may be modified by the operating system.
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A hard reset is generated at power on, by the F1 key or via a write to nextreg 0x02 with bit 1 set.
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A soft reset is generated by a hard reset, the F4 key or via a write to nextreg 0x02 with bit 0 set.
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NEXTREG REGISTER SPACE
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Generally a set bit indicates the property is asserted
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0x00 (00) => Machine ID
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(R)
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0000 1000 = EMULATORS
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//
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0000 1010 = ZX Spectrum Next
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1111 1010 = ZX Spectrum Next Anti-brick
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//
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1001 1010 = ZX Spectrum Next Core on UnAmiga Reloaded
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1010 1010 = ZX Spectrum Next Core on UnAmiga
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1011 1010 = ZX Spectrum Next Core on SiDi
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@@ -41,7 +56,7 @@
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** These signals are ignored if the multiface, divmmc, dma or external nmi master is active
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** Copper cannot clear these bits
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** An i/o trap could occur at the same time as mf / divmmc cause; always check this bit in nmi isr if important
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0x03 (03) => Machine Type
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(R)
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bit 7 = nextreg 0x44 second byte indicator
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@@ -69,9 +84,9 @@
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0x04 (04) => Config Mapping (config mode only, bootrom disabled)
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(W)
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bit 7 = Reserved, must be 0
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bits 6:0 = 16K SRAM bank mapped to 0x0000-0x3FFF (hard reset = 0)
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** Even multiplies of 256K are unreliable if storing data in sram for the next core started.
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bit 7 = Reserved, must be 0
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bits 6:0 = 16K SRAM bank mapped to 0x0000-0x3FFF (hard reset = 0)
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** Even multiplies of 256K are unreliable if storing data in sram for the next core started.
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0x05 (05) => Peripheral 1 Setting
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(R/W)
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@@ -90,17 +105,17 @@ Joystick modes:
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101 = MD 1 (3 or 6 button joystick port 0x1F)
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110 = MD 2 (3 or 6 button joystick port 0x37)
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111 = User Defined Keys Joystick
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* Joysticks can be placed in i/o mode via nextreg 0x0B.
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* Programming the user defined keys joystick is done through the ps2 keymap interface
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on nextreg 0x28, 0x29 and 0x2B:
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1. Write 128 to nextreg 0x28
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2. Write 0 (left joystick) or 16 (right joystick) to nextreg 0x29
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3. Write twelve bytes to nextreg 0x2B in order. The bytes correspond to the twelve
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buttons on an md pad (MODE=11 X Z Y START A C B U D L R=0)
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4. Each byte written identifies a key in the 8x7 membrane; bits 5:3 select the row
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and bits 2:0 select the column with 111 meaning no action
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* In kempston and md modes, excess buttons on a controller not read via ports will
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generate key input if so programmed
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* Joysticks can be placed in i/o mode via nextreg 0x0B.
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* Programming the user defined keys joystick is done through the ps2 keymap interface
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on nextreg 0x28, 0x29 and 0x2B:
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1. Write 128 to nextreg 0x28
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2. Write 0 (left joystick) or 16 (right joystick) to nextreg 0x29
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3. Write twelve bytes to nextreg 0x2B in order. The bytes correspond to the twelve
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buttons on an md pad (MODE=11 X Z Y START A C B U D L R=0)
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4. Each byte written identifies a key in the 8x7 membrane; bits 5:3 select the row
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and bits 2:0 select the column with 111 meaning no action
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* In kempston and md modes, excess buttons on a controller not read via ports will
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generate key input if so programmed
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0x06 (06) => Peripheral 2 Setting
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(R/W)
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@@ -183,16 +198,17 @@ generate key input if so programmed
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clock : 0 = hold high when clock becomes high, 1 = run *
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uart : 0 = redirect esp uart0 to joystick, 1 = redirect pi uart1 to joystick
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(Tx out on pin 7, Rx in from pin 9, CTS_n in from pin 6 **)
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The state of output pin 7 is stored internally in a register and is retained across changing
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modes and while i/o mode is disabled. While in i/o mode, keyboard joystick types (Sinclair,
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Cursor, etc) produce no readings but the current state of pins can still be read via the
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Kempston ports. When leaving i/o mode, joystick operation resumes after ~64 scan lines
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have passed.
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* CTC channel 3 is currently used to drive pin 7 in clock mode. Freq = Fctc3 / 2.
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** CTS_n is only active if the seleced uart is in hw flow control mode.
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The state of output pin 7 is stored internally in a register and is retained across changing
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modes and while i/o mode is disabled. While in i/o mode, keyboard joystick types (Sinclair,
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Cursor, etc) produce no readings but the current state of pins can still be read via the
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Kempston ports. When leaving i/o mode, joystick operation resumes after ~64 scan lines
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have passed.
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* CTC channel 3 is currently used to drive pin 7 in clock mode. Freq = Fctc3 / 2.
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** CTS_n is only active if the seleced uart is in hw flow control mode.
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0x0E (14) => Core Version (sub minor number)
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(R) (see register 0x01 for the major and minor version number)
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(R)
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(see register 0x01 for the major and minor version number)
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0x0F (15) => Board ID
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(R)
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@@ -212,7 +228,7 @@ have passed.
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bit 7 = Start selected core
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bits 6:5 = Reserved, must be 0
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bits 4:0 = Core ID 0-31 (config mode only) *
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* A write of an out of range core id is ignored; this is the preferred way to determine max id
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* A write of an out of range core id is ignored; this is the preferred way to determine max id
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0x11 (17) => Video Timing (writable in config mode only)
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(R/W)
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@@ -339,8 +355,8 @@ have passed.
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bit 6 = ula
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bits 5:4 = reserved
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bits 3:0 = ctc 3:0
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* Set bits on R indicate whether an interrupt occurred or is pending (alias of bits in NR 0xC8 - 0xCA)
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* Set bits on W always generate a maskable interrupt ignoring enables (NR 0xC4 - 0xC6)
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* Set bits on R indicate whether an interrupt occurred or is pending (alias of bits in NR 0xC8 - 0xCA)
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* Set bits on W always generate a maskable interrupt ignoring enables (NR 0xC4 - 0xC6)
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0x22 (34) => Line Interrupt control
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(R/W)
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@@ -349,7 +365,7 @@ have passed.
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bit 2 = Disables ula interrupt (soft reset = 0) **
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bit 1 = Enables line Interrupt (soft reset = 0) **
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bit 0 = MSB of line interrupt value (soft reset = 0)
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** Aliases of interrupt enable bits in nextreg 0xC4
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** Aliases of interrupt enable bits in nextreg 0xC4
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0x23 (35) => Line Interrupt Value LSB
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(R/W)
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@@ -383,7 +399,7 @@ have passed.
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(W)
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bits 7:1 = Reserved, must be 0
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bit 0 = MSB data
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* Not currently used by hardware, write 0
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* Not currently used by hardware, write 0
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0x2B (43) => PS/2 Keymap Data LSB
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(W) (write causes the data to be written and auto-increments the keymap address)
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@@ -449,23 +465,28 @@ have passed.
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0x35 (53) => Sprite Attribute 0
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0x75 (117) => Sprite Attribute 0 with automatic post increment of Sprite Number
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(W) See documentation at https://www.specnext.com/sprites/
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(W)
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See documentation at https://www.specnext.com/sprites/
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0x36 (54) => Sprite Attribute 1
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0x76 (118) => Sprite Attribute 1 with automatic post increment of Sprite Number
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(W) See documentation at https://www.specnext.com/sprites/
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(W)
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See documentation at https://www.specnext.com/sprites/
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0x37 (55) => Sprite Attribute 2
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0x77 (119) => Sprite Attribute 2 with automatic post increment of Sprite Number
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(W) See documentation at https://www.specnext.com/sprites/
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(W)
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See documentation at https://www.specnext.com/sprites/
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0x38 (56) => Sprite Attribute 3
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0x78 (120) => Sprite Attribute 3 with automatic post increment of Sprite Number
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(W) See documentation at https://www.specnext.com/sprites/
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(W)
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See documentation at https://www.specnext.com/sprites/
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0x39 (57) => Sprite Attribute 4
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0x79 (121) => Sprite Attribute 4 with automatic post increment of Sprite Number
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(W) See documentation at https://www.specnext.com/sprites/
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(W)
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See documentation at https://www.specnext.com/sprites/
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0x40 (64) => Palette Index
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(R/W)
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@@ -719,46 +740,51 @@ have passed.
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bit 0 = MSB of scroll amount
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0x75 (117) => Sprite Attribute 0 with automatic post increment of Sprite Number
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(W) see nextreg 0x35
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(W)
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see nextreg 0x35
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0x76 (118) => Sprite Attribute 1 with automatic post increment of Sprite Number
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(W) see nextreg 0x36
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(W)
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see nextreg 0x36
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0x77 (119) => Sprite Attribute 2 with automatic post increment of Sprite Number
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(W) see nextreg 0x37
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(W)
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see nextreg 0x37
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0x78 (120) => Sprite Attribute 3 with automatic post increment of Sprite Number
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(W) see nextreg 0x38
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(W)
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see nextreg 0x38
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0x79 (121) => Sprite Attribute 4 with automatic post increment of Sprite Number
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(W) see nextreg 0x39
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(W)
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see nextreg 0x39
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0x7F (127) => User Register 0
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(R/W)
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bits 7:0 = Unused storage available to the user (soft reset = 0xff)
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NEXTREG 0x80 AND HIGHER ARE INACCESSIBLE TO THE COPPER
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// NEXTREG 0x80 AND HIGHER ARE INACCESSIBLE TO THE COPPER
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0x80 (128) => Expansion Bus Enable
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(R/W) (hard reset = 0)
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IMMEDIATE
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bit 7 = 1 to enable the expansion bus
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bit 6 = 1 to enable romcs rom replacement from divmmc banks 14/15
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bit 5 = 1 to disable i/o cycles & ignore iorqula
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bit 4 = 1 to disable memory cycles & ignore romcs
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AFTER SOFT RESET (copied into bits 7-4)
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bit 3 = 1 to enable the expansion bus
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bit 2 = 1 to enable romcs rom replacement from divmmc banks 14/15
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bit 1 = 1 to disable i/o cycles & ignore iorqula
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bit 0 = 1 to disable memory cycles & ignore romcs
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IMMEDIATE
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bit 7 = 1 to enable the expansion bus
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bit 6 = 1 to enable romcs rom replacement from divmmc banks 14/15
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bit 5 = 1 to disable i/o cycles & ignore iorqula
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bit 4 = 1 to disable memory cycles & ignore romcs
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AFTER SOFT RESET (copied into bits 7-4)
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bit 3 = 1 to enable the expansion bus
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bit 2 = 1 to enable romcs rom replacement from divmmc banks 14/15
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bit 1 = 1 to disable i/o cycles & ignore iorqula
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bit 0 = 1 to disable memory cycles & ignore romcs
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0x81 (129) => Expansion Bus Control
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(R/W) (hard reset = 0)
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bit 7 = 1 if ROMCS is asserted on the expansion bus (read only)
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bit 6 = 1 to allow peripherals to override the ULA on some even port reads (rotronics wafadrive)
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bit 5 = 1 to disable expansion bus nmi debounce (opus discovery)
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bit 4 = 1 to propagate the max cpu clock at all times including when the expansion bus is off
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bits 1-0 = max cpu speed when the expansion bus is on (currently fixed at 00 = 3.5MHz)
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bit 7 = 1 if ROMCS is asserted on the expansion bus (read only)
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bit 6 = 1 to allow peripherals to override the ULA on some even port reads (rotronics wafadrive)
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bit 5 = 1 to disable expansion bus nmi debounce (opus discovery)
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bit 4 = 1 to propagate the max cpu clock at all times including when the expansion bus is off
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bits 1-0 = max cpu speed when the expansion bus is on (currently fixed at 00 = 3.5MHz)
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0x85,0x84,0x83,0x82 (133-130) => Internal Port Decoding Enables (0x85 is MSB) (soft reset if bit 31 = 1, hard reset if bit 31 = 0 : all 1)
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0x89,0x88,0x87,0x86 (137-134) => Expansion Bus Decoding Enables (0x89 is MSB) (soft reset if bit 31 = 0, hard reset if bit 31 = 1 : all 1)
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@@ -820,36 +846,36 @@ bits 1-0 = max cpu speed when the expansion bus is on (currently fixed at 00 = 3
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0x8C (140) => Alternate ROM
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(R/W) (hard reset = 0)
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IMMEDIATE
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IMMEDIATE
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bit 7 = 1 to enable alt rom
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bit 6 = 1 to make alt rom visible only during writes, otherwise replaces rom during reads
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bit 5 = 1 to lock ROM1 (48K rom)
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bit 4 = 1 to lock ROM0 (128K rom)
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AFTER SOFT RESET (copied into bits 7-4)
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AFTER SOFT RESET (copied into bits 7-4)
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bit 3 = 1 to enable alt rom
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bit 2 = 1 to make alt rom visible only during writes, otherwise replaces rom during reads
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bit 1 = 1 to lock ROM1 (48K rom)
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bit 0 = 1 to lock ROM0 (128K rom)
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The locking mechanism also applies if the alt rom is not enabled. For the +3 and zx next, if the two lock bits are not
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zero, then the corresponding rom page is locked in place. Other models use the bits to preferentially lock the corresponding
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48K rom or the 128K rom.
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The locking mechanism also applies if the alt rom is not enabled. For the +3 and zx next, if the two lock bits are not
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zero, then the corresponding rom page is locked in place. Other models use the bits to preferentially lock the corresponding
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48K rom or the 128K rom.
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0x8E (142) => Spectrum 128K Memory Mapping
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(R/W)
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bit 7 = port 0xdffd bit 0 \ RAM
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bits 6:4 = port 0x7ffd bits 2:0 / bank 0-15
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R bit 3 = 1
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W bit 3 = 1 to change RAM bank, 0 = no change to mmu6 / mmu7 / RAM bank in ports 0x7ffd, 0xdffd
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R bit 3 = 1
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W bit 3 = 1 to change RAM bank, 0 = no change to mmu6 / mmu7 / RAM bank in ports 0x7ffd, 0xdffd
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bit 2 = port 0x1ffd bit 0 paging mode
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If bit 2 = paging mode = 0 (normal)
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If bit 2 = paging mode = 0 (normal)
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bit 1 = port 0x1ffd bit 2 \ ROM
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bit 0 = port 0x7ffd bit 4 / select
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If bit 2 = paging mode = 1 (special allRAM)
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If bit 2 = paging mode = 1 (special allRAM)
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bit 1 = port 0x1ffd bit 2 \ all
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bit 0 = port 0x1ffd bit 1 / RAM
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Writes can affect all ports 0x7ffd, 0xdffd, 0x1ffd
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Writes always change the ROM / allRAM mapping
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Writes immediately change the current mmu mapping as if by port write
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Writes can affect all ports 0x7ffd, 0xdffd, 0x1ffd
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Writes always change the ROM / allRAM mapping
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Writes immediately change the current mmu mapping as if by port write
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0x8F (143) => Memory Mapping Mode
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(R/W) (hard reset = 0)
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@@ -859,10 +885,10 @@ Writes immediately change the current mmu mapping as if by port write
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01 = Reserved
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10 = Pentagon 512K
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11 = Pentagon 1024K (limited to 768K on 1MB machines)
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* Standard ZX 128K +3 = principally ports 0x7ffd, 0xdffd, 0x1ffd
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* Pentagon 512K = principally port 0x7ffd
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* Pentagon 1024K = principally ports 0x7ffd, 0xeff7
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** The mapping modes affect how ports 0x7ffd, 0xdffd, 0x1ffd and 0xeff7 carry out memory paging, see ports.txt
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* Standard ZX 128K +3 = principally ports 0x7ffd, 0xdffd, 0x1ffd
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* Pentagon 512K = principally port 0x7ffd
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* Pentagon 1024K = principally ports 0x7ffd, 0xeff7
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** The mapping modes affect how ports 0x7ffd, 0xdffd, 0x1ffd and 0xeff7 carry out memory paging, see ports.txt
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0x93,0x92,0x91,0x90 (147-144) => PI GPIO Output Enable (0x93 is MSB)
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(R/W)
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@@ -883,7 +909,7 @@ Writes immediately change the current mmu mapping as if by port write
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bit 3 = Enable I2C on GPIO 2,3 (override gpio) (soft reset = 0)
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bits 2:1 = Reserved, must be 0
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bit 0 = Enable SPI on GPIO 7,8,9,10,11 (overrides gpio) (soft reset = 0)
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* GPIO 16,17 will function as rtr_n and cts_n if the uart is in hw flow control mode
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* GPIO 16,17 will function as rtr_n and cts_n if the uart is in hw flow control mode
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0xA2 (162) => PI I2S Audio Control
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(R/W)
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@@ -926,7 +952,7 @@ Writes immediately change the current mmu mapping as if by port write
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bit 2 = 1 if DOWN pressed
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bit 1 = 1 if LEFT pressed
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bit 0 = 1 if RIGHT pressed
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* Nextreg 0x68 bit 4 stops extended keys from making entries in the 8x5 matrix
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* Nextreg 0x68 bit 4 stops extended keys from making entries in the 8x5 matrix
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0xB1 (177) => Extended Keys 1
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(R)
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@@ -938,7 +964,7 @@ Writes immediately change the current mmu mapping as if by port write
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bit 2 = 1 if GRAPH pressed
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bit 1 = 1 if CAPS LOCK pressed
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bit 0 = 1 if EXTEND pressed
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* Nextreg 0x68 bit 4 stops extended keys from making entries in the 8x5 matrix
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* Nextreg 0x68 bit 4 stops extended keys from making entries in the 8x5 matrix
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0xB2 (178) => Extended MD Pad Buttons
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(R)
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@@ -1004,7 +1030,7 @@ Writes immediately change the current mmu mapping as if by port write
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bit 3 = Enable stackless nmi response**
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bits 2:1 = Current Z80 interrupt mode 0,1,2 (read only, write ignored)
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bit 0 = Maskable interrupt mode: pulse (0) or hw im2 mode (1)
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* In hw im2 mode the interrupt vector generated is:
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* In hw im2 mode the interrupt vector generated is:
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bits 7:5 = nextreg 0xC0 bits 7:5
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bits 4:1 = 0 line interrupt (highest priority)
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= 1 uart0 Rx
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@@ -1014,23 +1040,22 @@ Writes immediately change the current mmu mapping as if by port write
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= 12 uart0 Tx
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= 13 uart1 Tx (lowest priority)
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bit 0 = 0
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* In hw im2 mode the expansion bus is the lowest priority interrupter
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and if no vector is supplied externally then 0xFF is generated.
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** The return address pushed during an nmi acknowledge cycle will
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be written to nextreg instead of memory (the stack pointer will
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be decremented) and the first RETN after the acknowledge will
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take its return address from nextreg instead of memory (the stack
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pointer will be incremented). If bit 3 = 0 and in other
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circumstances, RETN functions normally.
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* In hw im2 mode the expansion bus is the lowest priority interrupter
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and if no vector is supplied externally then 0xFF is generated.
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** The return address pushed during an nmi acknowledge cycle will
|
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be written to nextreg instead of memory (the stack pointer will
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be decremented) and the first RETN after the acknowledge will
|
||||
take its return address from nextreg instead of memory (the stack
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||||
pointer will be incremented). If bit 3 = 0 and in other
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circumstances, RETN functions normally.
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0xC2 (194) => NMI Return Address LSB
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(R/W) (soft reset = 0)
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0xC3 (195) => NMI Return Address MSB
|
||||
(R/W) (soft reset = 0)
|
||||
|
||||
The return address written during an nmi acknowledge cycle is
|
||||
always stored in these registers.
|
||||
The return address written during an nmi acknowledge cycle is
|
||||
always stored in these registers.
|
||||
|
||||
--
|
||||
|
||||
@@ -1040,8 +1065,8 @@ always stored in these registers.
|
||||
bits 6:2 = Reserved must be 0
|
||||
bit 1 = Line **
|
||||
bit 0 = ULA **
|
||||
* If a device interrupt is disabled, it enters a polled mode
|
||||
** Aliases of interrupt enable bits in nextreg 0x22
|
||||
* If a device interrupt is disabled, it enters a polled mode
|
||||
** Aliases of interrupt enable bits in nextreg 0x22
|
||||
|
||||
0xC5 (197) => INT EN 1
|
||||
(R/W) (soft reset = 0)
|
||||
@@ -1053,7 +1078,7 @@ always stored in these registers.
|
||||
bit 2 = ctc channel 2 zc/to
|
||||
bit 1 = ctc channel 1 zc/to
|
||||
bit 0 = ctc channel 0 zc/to
|
||||
* If a device interrupt is disabled, it enters a polled mode
|
||||
* If a device interrupt is disabled, it enters a polled mode
|
||||
|
||||
|
||||
0xC6 (198) => INT EN 2
|
||||
@@ -1066,8 +1091,8 @@ always stored in these registers.
|
||||
bit 2 = UART0 Tx empty
|
||||
bit 1 = UART0 Rx near full \ shared
|
||||
bit 0 = UART0 Rx available / interrupt
|
||||
* Rx near full overrides Rx available
|
||||
* If a device interrupt is disabled, it enters a polled mode
|
||||
* Rx near full overrides Rx available
|
||||
* If a device interrupt is disabled, it enters a polled mode
|
||||
|
||||
0xC7 (199) => Reserved, write 0
|
||||
|
||||
@@ -1078,8 +1103,8 @@ always stored in these registers.
|
||||
bits 7:2 = Reserved must be 0
|
||||
bit 1 = Line
|
||||
bit 0 = ULA
|
||||
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
|
||||
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the
|
||||
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
|
||||
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the
|
||||
interrupt pending condition is cleared
|
||||
|
||||
0xC9 (201) => INT Status 1
|
||||
@@ -1092,8 +1117,8 @@ always stored in these registers.
|
||||
bit 2 = ctc channel 2 zc/to
|
||||
bit 1 = ctc channel 1 zc/to
|
||||
bit 0 = ctc channel 0 zc/to
|
||||
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
|
||||
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the
|
||||
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
|
||||
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the
|
||||
interrupt pending condition is cleared
|
||||
|
||||
0xCA (202) => INT Status 2
|
||||
@@ -1106,8 +1131,8 @@ always stored in these registers.
|
||||
bit 2 = UART0 Tx empty
|
||||
bit 1 = UART0 Rx half full \ shared
|
||||
bit 0 = UART0 Rx available / interrupt
|
||||
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
|
||||
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the
|
||||
* (R) Set bits indicate the device generated an interrupt in the past or an interrupt is pending
|
||||
* (W) Set bits clear the status. In hw im2 mode the status will continue to read as set until the
|
||||
interrupt pending condition is cleared
|
||||
|
||||
0xCB (203) => Reserved, write 0xFF
|
||||
@@ -1119,7 +1144,7 @@ always stored in these registers.
|
||||
bit 7 = NMI
|
||||
bit 1 = Line
|
||||
bit 0 = ULA
|
||||
* Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode
|
||||
* Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode
|
||||
|
||||
0xCD (205) => DMA INT EN 1
|
||||
(R/W) (soft reset = 0)
|
||||
@@ -1131,7 +1156,7 @@ always stored in these registers.
|
||||
bit 2 = ctc channel 2 zc/to
|
||||
bit 1 = ctc channel 1 zc/to
|
||||
bit 0 = ctc channel 0 zc/to
|
||||
* Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode
|
||||
* Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode
|
||||
|
||||
0xCE (206) => DMA INT EN 2
|
||||
(R/W) (soft reset = 0)
|
||||
@@ -1143,7 +1168,7 @@ always stored in these registers.
|
||||
bit 2 = UART0 Tx empty
|
||||
bit 1 = UART0 Rx half full \ shared
|
||||
bit 0 = UART0 Rx available / interrupt
|
||||
* Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode
|
||||
* Set bits indicate the corresponding interrupt will interrupt a dma operation when in hw im2 mode
|
||||
|
||||
0xCF (207) => Reserved, write 0
|
||||
|
||||
@@ -1157,8 +1182,8 @@ progress is made in the main program.
|
||||
(R/W) (soft reset = 0)
|
||||
bits 7:1 = Reserved must be zero
|
||||
bit 0 = 1 to enable +3 FDC traps on ports 0x2ffd and 0x3ffd
|
||||
* An i/o trap generates a multiface nmi and is indicated in nextreg 0x02
|
||||
* Traps cannot be triggered by the dma or while the multiface, divmmc or external nmi is active
|
||||
* An i/o trap generates a multiface nmi and is indicated in nextreg 0x02
|
||||
* Traps cannot be triggered by the dma or while the multiface, divmmc or external nmi is active
|
||||
|
||||
0xD9 (217) => I/O Trap Write (experimental)
|
||||
(R/W)
|
||||
@@ -1169,7 +1194,7 @@ progress is made in the main program.
|
||||
1 = port_2ffd read
|
||||
2 = port_3ffd read
|
||||
3 = port_3ffd write
|
||||
* If nextreg 0x02 bit 4 indicates an i/o cycle was trapped, this register indicates the cause
|
||||
* If nextreg 0x02 bit 4 indicates an i/o cycle was trapped, this register indicates the cause
|
||||
|
||||
--
|
||||
|
||||
@@ -1205,28 +1230,26 @@ progress is made in the main program.
|
||||
bit 7 = 1 to enter select mode (write has no other effect)
|
||||
bit 6 = 1 to reset XADC (RESET)
|
||||
bit 0 = 1 to start conversion (CONVST)
|
||||
* Re-enter select mode at any time by writing to the register with bit 7 set
|
||||
* Select a device to communicate with by writing to the register with bits 6 & 7 set
|
||||
* Exit select mode by writing zero to bit 7; thereafter the particular device is attached to the nextreg
|
||||
* Re-enter select mode at any time by writing to the register with bit 7 set
|
||||
* Select a device to communicate with by writing to the register with bits 6 & 7 set
|
||||
* Exit select mode by writing zero to bit 7; thereafter the particular device is attached to the nextreg
|
||||
|
||||
0xF8 (248) => XADC REG
|
||||
(R/W Issue 4 Only) (hard reset = 0)
|
||||
bit 7 = 1 to write to XADC DRP port, 0 to read from XADC DRP port **
|
||||
bits 6:0 = XADC DRP register address DADDR
|
||||
* An XADC register read or write is initiated by writing to this register
|
||||
* There must be at least six 28 MHz cycles after each r/w to this register
|
||||
** Reads as 0
|
||||
bit 7 = 1 to write to XADC DRP port, 0 to read from XADC DRP port **
|
||||
bits 6:0 = XADC DRP register address DADDR
|
||||
* An XADC register read or write is/ initiated by writing to this register
|
||||
* There must be at least six 28 MHz cycles after each r/w to this register
|
||||
** Reads as 0
|
||||
|
||||
0xF9 (249) => XADC D0
|
||||
(R/W Issue 4 Only) (hard reset = 0)
|
||||
bits 7:0 = LSB data connected to XADC DRP data bus D7:0
|
||||
* DRP reads store result here, DRP writes take value from here
|
||||
bits 7:0 = LSB data connected to XADC DRP data bus D7:0
|
||||
* DRP reads store result here, DRP writes take value from here
|
||||
|
||||
0xFA (250) => XADC D1
|
||||
(R/W Issue 4 Only) (hard reset = 0)
|
||||
bits 7:0 = MSB data connected to XADC DRP data bus D15:8
|
||||
DRP reads store result here, DRP writes take value from here
|
||||
|
||||
--
|
||||
bits 7:0 = MSB data connected to XADC DRP data bus D15:8
|
||||
* DRP reads store result here, DRP writes take value from here
|
||||
|
||||
0xFF (255) => Reserved for internal use
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -9,6 +9,11 @@ interface RegisterBrowserProps {
|
||||
registers: Register[];
|
||||
}
|
||||
|
||||
/**
|
||||
* Renders the access details for a register, including its description, operations, and notes.
|
||||
* @param access The register access data to render.
|
||||
* @returns A React component that displays the register access details.
|
||||
*/
|
||||
export function renderAccess(access: RegisterAccess) {
|
||||
const renderTooltip = (notes: Note[]) => (
|
||||
<Tooltip id="tooltip">
|
||||
@@ -56,6 +61,11 @@ export function renderAccess(access: RegisterAccess) {
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* A component for browsing and searching through a list of registers.
|
||||
* @param registers An array of Register objects to display.
|
||||
* @returns A React component that allows users to browse and search registers.
|
||||
*/
|
||||
export default function RegisterBrowser({ registers }: RegisterBrowserProps) {
|
||||
const [searchTerm, setSearchTerm] = useState('');
|
||||
|
||||
|
||||
@@ -4,6 +4,12 @@ import { Container, Row, Col, Card, Tabs, Tab } from 'react-bootstrap';
|
||||
import { Register } from './types';
|
||||
import { renderAccess } from './RegisterBrowser';
|
||||
|
||||
/**
|
||||
* A client-side component that displays the details of a single register.
|
||||
* @param register The register object to display.
|
||||
* @param defaultActiveKey The default active tab to display.
|
||||
* @returns A React component that displays the register details.
|
||||
*/
|
||||
export default function RegisterDetailClient({
|
||||
register,
|
||||
defaultActiveKey,
|
||||
|
||||
@@ -3,6 +3,11 @@ import path from 'path';
|
||||
import RegisterBrowser from './RegisterBrowser';
|
||||
import { Register, RegisterAccess } from './types';
|
||||
|
||||
/**
|
||||
* Parses the content of the nextreg.txt file and returns an array of register objects.
|
||||
* @param fileContent The content of the nextreg.txt file.
|
||||
* @returns A promise that resolves to an array of Register objects.
|
||||
*/
|
||||
async function parseNextReg(fileContent: string): Promise<Register[]> {
|
||||
const registers: Register[] = [];
|
||||
const paragraphs = fileContent.split(/\n\s*\n/);
|
||||
|
||||
Reference in New Issue
Block a user